This invention relates generally to semiconductor integrated circuit memory devices and more particularly, it relates to a semiconductor integrated circuit memory device having a test logic circuit structure for performing a measurement operation on memory arrays of the semiconductor memory circuit device. Specifically, the present invention is directed to a test logic circuit structure used in a semiconductor memory of an erasable programmable read-only memory (EPROM) or electrically erasable programmable read-only memory (EEPROM or E.sup.2 PROM) type for measuring the threshold of an array cell which is less than zero or is less than the threshold of a reference cell without requiring the use of negative supply potentials.
In recent years, the semiconductor integrated circuit memory devices, especially MOS integrated circuits utilizing MOS transistors, are becoming more and more microminiaturized by reducing the size of the memory cell transistors and thus the memory chips so as to increase the memory capacity for a given chip area. The bit density for such memory devices having a high memory capacity in the last few years has reached IM bits on the memory chips now in production. This has been achieved usually through the fabrication of the depth of the source and drain regions of the MOS transistors to be shallower or by decreasing the length of the gate region. The thickness of the gate insulation film is also reduced. As a result of the scaling of the MOS transistor devices, the parametric variations from transistor device to transistor device may tend to increase. This would certainly be the case when considering the parametric variations occurring in the number of transistors in large memory arrays. Insulation film thickness variations (physical), line width variations and defects could easily be attributed to these parametric variations.
With these physical variations, the programming and erasing characteristics of an EEPROM or more specifically a single transistor Flash EPROM (Flash EEPROM) can vary from transistor device to transistor device in the same memory array. For the single transistor Flash EPROM, it is particularly important to maintain tight control over the threshold voltage distributions of erased cells. It is also important to maintain the threshold voltages of all erased cells to be greater than zero. If the threshold voltage V.sub.T of the cell on a given column (bit line) becomes less than zero, then there will be column leakage thereby rendering the cells in this column increasingly more difficult to program. Under this condition, there is brought about a disadvantage that the data programming characteristic of the memory cell is deteriorated so as to cause endurance failures. Consequently, the number of times that the memory cell may be re-programmed is significantly reduced.
As is generally known, a positive power source voltage, typically +5.0 volts, is applied to the gate of the MOS transistor of the selected memory cell and the non-selected memory cell is provided with a gate voltage of zero volts. However, when the threshold voltage drops abnormally to a negative value the memory cell not selected will be rendered conductive. In order to turn- o off the MOS transistor having the negative threshold, a negative power source voltage is required. It is generally undesirable to use negative power source voltages for the MOS integrated circuits from a practical design point of view.
In order to fabricate memory devices of the EPROM or EEPROM type with a high yield which have a large memory capacity IM bits) and a high reliability (i.e., does not have endurance failures caused by negative thresholds), there has arisen a need to provide a test logic circuit structure for measuring the threshold voltages of each memory cell transistor in the memory device to determine if it is negative without requiring a negative supply voltage, thereby enhancing its production yield. Therefore, it is important to verify the threshold voltages of the memory cell transistors so as to avoid causing the entire chip to be usable due to a single flaw in its fabrication. In the event that memory cell transistors are found to have negative thresholds, such defective memory cells can be replaced by a redundancy circuity which can be easily implemented by those skilled in the art. In view of the large number of memory cells on the single memory chip that must be tested, it would be expedient that the test logic circuit structure be capable of operating at a very high speed.